1. Field of the Invention
The present invention relates to a microcomputer logic development device used when developing a built-in microcomputer, more particularly relates to a microcomputer logic development device adding a RAM monitor function.
2. Description of the Related Art
Electronic control units (ECU) for engine control and other electronic control devices have to be improved in performance along with enactment of tougher emission controls and other legal regulations and improvements in microcomputer performance. Therefore, electronic control devices have to be improved every year. New applications are being developed in advance of current levels of electronic control device performance (hereinafter called “advance logic”).
Such advance logic is often developed targeting the next generation of microcomputers offering improved performance over the present. However, at the time of development of advance logic, there are no actual electronic control devices with the next generation microcomputers built in them.
The inventors previously proposed a microcomputer logic development device able to provide the processing performance required for processing advance logic for CPU functions and able to provide resources matching the advanced device from peripheral resources of the microcomputer (for example, see Japanese Unexamined Patent Publication (Kokai) No. 2003-167756 and Japanese Unexamined Patent Publication (Kokai) No. 2004-013626).
With this microcomputer logic development device, it becomes possible to develop a built-in microcomputer able to realize advanced logic in a short time. At the same time, the microcomputer logic development device can be repeatedly utilized.
FIG. 1 will be used to explain the configuration of a conventional microcomputer logic development device. Note that FIG. 1 shows an embodiment of the present invention. Therefore, it should be understood that FIG. 1 includes parts of a configuration not existing in a conventional device.
The microcomputer logic development device 1 is comprised of a mother board 2 realizing functions corresponding to a microcomputer core, a core board 3 realizing functions corresponding to microcomputer resources, and an interface board 4 realizing functions corresponding to ECU hardware.
The mother board 2 and core board 3 are connected by a PCI bus 12 and communicate data of I/O information. The mother board 2 and core board 3 have I/O driver software 6 and 7 loaded in them and control communication of data of the I/O information.
Next, one of the peripheral functions of a microcomputer is the RAM monitor function. This is a function for extracting RAM data of an address of the microcomputer and returning it to an externally connected RAM measurement device when an address is designated from the RAM measurement device.
FIG. 2 shows the configuration of a RAM monitor in a built-in microcomputer of an ordinary ECU.
In an ECU built-in microcomputer 24, the CPU 25 is connected with the RAM 27 and ROM 28 through an internal bus 26. The internal bus 26 is connected through a direct memory access (DMA) 29 to the RAM monitor function 30.
The RAM measurement device 14 is connected to a RAM monitor function 30. The RAM measurement device 14 is known, designates RAM addresses and sends them to the monitor function 30, and stores the RAM data returned from the monitor function 30. The stored data is displayed processed to a suitable display format.
The RAM monitor function 30 has a non-brake debugging (NBD) function. The RAM monitor function 30 is one of the on-chip debugging functions. It sets the sampling time in accordance with a specific communication protocol and, when requesting an address of the memory to be monitored, operates the DMA 29 and extracts and returns the data of the requested address.
The DMA 29 is a function enabling the memory 1 to be directly read and written without software processing. Therefore, in the illustrated built-in microcomputer 24, it is possible to monitor the RAM without stopping software in the middle of processing. Further, the DMA 29 is a hardware structure, so can perform processing at a high speed.
When the RAM measurement device 14 is applied to the microcomputer logic development device 1 shown in FIG. 1, it is necessary to realize the part of the RAM monitor function 30 by a core board separate from the mother board. In this case, the processing when receiving a request for an address from the RAM measurement device 14 until extracting and returning data through the PCI bus is executed by software processing, so high speed response is impossible like in the conventional device shown in FIG. 2.